The disclosure herein is directed to integrated circuits, and more particularly, voltage conversion circuits in the form of integrated circuits.
With the expansion of mobile product markets, there is additional need for power economization in the mobile devices because they must operate optimally for extended periods of time and with limited battery capacity. As a result, many techniques for power economization in mobile devices have been proposed. One proposal is to supply different voltages to functional blocks of the mobile apparatuses. In this configuration, low-functional blocks are supplied with lower voltages, and high-functional blocks are supplied with higher voltages. However, as the different voltages are applied to the functional blocks, leakage currents increase. It therefore becomes difficult to ensure normal operational performance in interfacing with the functional blocks due to the resulting voltage differences between the external and internal voltages.
FIG. 1 shows a conventional voltage conversion circuit (or level shifting circuit) for interfacing with the functional blocks at various voltage levels.
Another technique implemented for reducing power consumption in mobile apparatuses is dynamic voltage-scaling (DVS). DVS operates by varying and adjusting voltages, which are applied to the functional blocks, in accordance with operational conditions. For instance, high voltages are used in normal states of operation, and low voltages are used in standby states. However, using DVS produces an operating voltage for a functional block which will be higher or lower than operating voltages in peripheral blocks.
In general, the transition delays arising from operations of signal transmission are determined by the gate-source voltages of the transistors in the signal transmission circuit. For example, as illustrated in FIG. 2A, when an input signal IN1 of an inverter goes up to a first voltage VDD1 of high level from a ground voltage of low level, the NMOS transistor M12 is turned on. During this, an output signal OUT1 of the inverter goes down to a low level of the ground voltage from a high level of the first voltage VDD1, where the high-to-low transition of the output signal OUT1 is determined by a gate-source voltage of the NMOS transistor M12. Also, as illustrated in FIG. 2B, when an input signal IN2 of an inverter rises up to a second voltage VDD2 of high level from the ground voltage of low level, the NMOS transistor M14 is turned on. During this, an output signal OUT2 of the inverter falls down to a low level of the ground voltage from a high level of the first voltage VDD1, where the high-to-low transition of the output signal OUT2 is determined by a gate-source voltage of the NMOS transistor M14.
Assuming that the first voltage VDD1 is higher than the second voltage VDD2, the high-to-low transition of the output signal OUT1 occurs before that of the output signal OUT2 because the gate-source voltage of the NMOS transistor M12 is higher than that of the NMOS transistor M14.
Hereinafter, the high-to-low transition of the output signal OUT1 will be referred to as ‘fast transition’, and the high-to-low transition of the output signal OUT2 will be referred to as ‘slow transition’, under the condition that the first voltage VDD1 is higher than the second voltage VDD2. As is known in the art, a signal delay time of fast transition is shorter than that of slow transition.
On the other hand, as illustrated in FIG. 2C, when an input signal IN3 of an inverter goes down to the ground voltage of low level from the first voltage VDD1 of high level, the PMOS transistor M15 is turned on. During this, an output signal OUT3 of the inverter goes up to a high level of the first voltage VDD1 from a low level of the ground voltage, where the low-to-high transition of the output signal OUT1 is determined by a gate-source voltage of the PMOS transistor M15. Also, as illustrated in FIG. 2D, when an input signal IN4 of an inverter goes to the ground voltage of low level from the second voltage VDD2 of high level, the PMOS transistor M17 is turned on. During this, an output signal OUT4 of the inverter goes up to a high level of the first voltage VDD1 from a low level of the ground voltage, where the low-to-high transition of the output signal OUT4 is determined by a gate-source voltage of the PMOS transistor M17.
Here, according to the aforementioned assumption, i.e., if VDD1>VDD2, the low-to-high transition of the output signal OUT3, as well as the low-to-high transition of the output signal OUT4, are regarded as operating in the fast transition because the gate-source voltages of the PMOS transistors M15 and M17 rise up to VDD1 at maximum.
As can be understood from the aforementioned, when the first voltage VDD1 is lower than the second voltage VDD2, the output signals, OUT1, OUT3, and OUT4, are regarded as operating in the slow transition because the maximum gate-source voltages of the transistors are VDD1. However, the output signal OUT2 is regarded as operating in the fast transition because the maximum gate-source voltage of the transistor is VDD2.
As mentioned above, using DVS produces operating voltages for the functional blocks which are higher or lower than other voltages in peripheral blocks. This produces generated distortions of transfer signals (i.e., clock signals) and duty ratio. Now, variations in duty ratio related to the characteristics of transition delays will be described.
Referring to FIG. 1, if VDD1 is higher than the second voltage VDD2, when a signal falls from high to low and VDD1 is applied at an input terminal T1, a PMOS transistor M1, an NMOS transistor M5, a PMOS transistor M4, and an NMOS transistor M10 are turned on. During this, the transistors, M1, M5, M4, and M10, are operating in the conditions of fast, fast, slow, and slow (FFSS) transitions, respectively. Otherwise, when a signal rises from low to high and VDD1 is applied to an input terminal T1, a NMOS transistor M2, a PMOS transistor M7, an NMOS transistor M6, and a PMOS transistor M9 are turned on. During this, the transistors, M2, M7, M6, and M9, are operating in the conditions of fast, fast, fast, and slow (FFFS) transitions, respectively.
If the first voltage VDD1 is lower than the second voltage VDD2, when a signal falls from high to low and VDD1 is applied to an input terminal T1, the PMOS transistor M1, the NMOS transistor M5, the PMOS transistor M4, and the NMOS transistor M10 are turned on. During this, the transistors, M1, M5, M4, and M10, are operating in the conditions of slow, slow, fast, and fast (SSFF) transitions, respectively. Otherwise, when a signal rises from low to high and VDD1 is applied to an input terminal T1, the NMOS transistor M2, the PMOS transistor M7, the NMOS transistor M6, and the PMOS transistor M9 are turned on. During this, the transistors, M2, M7, M6, and M9, are operating in the conditions of slow, slow, slow, and fast (SSSF) transitions, respectively.
Hereinafter, a fast transition is represented by a symbol ‘F’ while a slow transition is represented by a ‘S’, with the variation patterns of transition being summarized in the following Table 1.
TABLE 1INVDD1 > VDD2VDD1 < VDD2HIGH→LOW (VDD1→GND)FFSSSSFFLOW→HIGH (GND→VDD1)FFFSSSSF
As can be seen from Table 1, the patterns of transition delay are changed by variations of the first and second voltages VDD1 and VDD2. While the down-transition delay pattern changes to ‘SSFF’ from ‘FFSS’, there is no variation in the down-transition delay characteristic as a whole. However, the up-transition delay pattern changes to ‘SSSF’ from ‘FFFS’, resulting in variation by 2F2S. This result of the up-transition delay means that there is variation of a signal (e.g., a clock signal) transferred through the level shifting circuit LS. For example, assuming that the first voltage VDD1 is higher than the second voltage VDD2 (VDD1>VDD2) and the duty ratio of the clock signal OUT_CLK therein is 50:50; the duty ratio of the clock signal OUT_CLK deviates by 50% from the condition of VDD1<VDD2, as shown in FIG. 3. This difference between duty ratios occurs as the down-transition delay is different from the up-transition delay in the pattern of variation when the first and second voltages VDD1 and VDD2 are changing.
As is well known in the art, the distortion of the clock duty ratio causes a clock skew effect in the circuit. The clock skew causes reduction of setup and hold margins. In summary, the clock skew generation results in a decrease of operation speed and decreased performance in the level shifting circuit or voltage conversion circuit.